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infineon technologies 1 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram 256 mbit synchronous dram the hyb39s256400/800/160dt(l) are four bank synchronous dram?s organized as 4 banks x 16mbit x4, 4 banks x 8mbit x8 and 4 banks x 4mbit x16 respectively. these synchronous devices achieve high speed data transfer rates for cas -latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. the chip is fabricated with infineon?s advanced 0.14 m 256mbit dram process technology. the device is designed to comply with all industry standards set for synchronous dram products, both electrically and mechanically. all of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard drams. a sequential and gapless data rate is possible depending on burst length, cas latency and speed grade of the device. auto refresh (cbr) and self refresh operation are supported. these devices operate with a single 3.3v +/- 0.3v power supply. all 256mbit components are available in tsopii-54 and tfbga-54 packages. high performance: fully synchronous to positive clock edge 0to70 c operating temperature four banks controlled by ba0 & ba1 programmable cas latency: 2 & 3 programmable wrap sequence: sequential or interleave programmable burst length: 1, 2, 4, 8 and full page multiple burst read with single write operation automatic and controlled precharge command -6 -7 -7.5 -8 units fck 166 143 133 125 mhz tck3 6 7 7.5 8 ns tac3 5 5.4 5.4 6 ns tck2 7.5 7.5 10 10 ns tac2 5.4 5.4 6 6 ns data mask for read / write control (x4, x8) data mask for byte control (x16) auto refresh (cbr) and self refresh power down and clock suspend mode 8192 refresh cycles / 64 ms (7,8 s) random column address every clk (1-nrule) single 3.3v +/- 0.3v power supply lvttl interface versions plastic packages: p-tsopii-54 400mil width (x4, x8, x16) chipsize packages: 54 ball tfbga (12 mm x 8 mm) -6 parts for pc166 3-3-3 operation -7 parts for pc133 2-2-2 operation -7.5 parts for pc133 3-3-3 operation -8 parts for pc100 2-2-2 operation
infineon technologies 2 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram ordering information pin description: type speed grade package description hyb 39s256400dt-6 pc166-333-520 p-tsop-54-2 (400mil) 166mhz 4b x 16m x 4 sdram hyb 39s256400dt-7 pc133-222-520 p-tsop-54-2 (400mil) 143mhz 4b x 16m x 4 sdram hyb 39s256400dt-7.5 pc133-333-520 p-tsop-54-2 (400mil) 133mhz 4b x 16m x 4 sdram hyb 39s256400dt-8 pc100-222-620 p-tsop-54-2 (400mil) 125mhz 4b x 16m x 4 sdram hyb 39s256800dt-6 pc166-333-520 p-tsop-54-2 (400mil) 166mhz 4b x 8m x 8 sdram hyb 39s256800dt-7 pc133-222-520 p-tsop-54-2 (400mil) 143mhz 4b x 8m x 8 sdram hyb 39s256800dt-7.5 pc133-333-520 p-tsop-54-2 (400mil) 133mhz 4b x 8m x 8 sdram hyb 39s256800dt-8 pc100-222-620 p-tsop-54-2 (400mil) 125mhz 4b x 8m x 8 sdram hyb 39s256160dt-6 pc166-333-520 p-tsop-54-2 (400mil) 166mhz 4b x 4m x 16 sdram hyb 39s256160dt-7 pc133-222-520 p-tsop-54-2 (400mil) 143mhz 4b x 4m x 16 sdram hyb 39s256160dt-7.5 pc133-333-520 p-tsop-54-2 (400mil) 133mhz 4b x 4m x 16 sdram hyb 39s256160dt-8 pc100-222-620 p-tsop-54-2 (400mil) 125mhz 4b x 4m x 16 sdram hyb39s256800dtl-x p-tsop-54-2 (400mil) 4b x 8m x 8 sdram low power versions (on request) hyb39s256160dtl-x p-tsop-54-2 (400mil) 4b x 4m x 16 sdram low power versions (on request) hyb39s256xx0dc(l)-x p-tfbga-54 (on request) clk clock input dqx data input /output cke clock enable dqm, ldqm, udqm data mask cs chip select v dd power (+3.3v) ras row address strobe v ss ground cas column address strobe v ddq power for dq?s (+ 3.3v) we write enable v ssq ground for dq?s a0-a12 address inputs nc not connected ba0, ba1 bank select
infineon technologies 3 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram pinouts (tsop-54) spp04126 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v dd dq0 a10/ap a0 a1 a2 a3 v dd v ddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 v dd ldqm cas we ras cs ba0 ba1 ba1 ba0 cs ras we cas n.c. v dd n.c. v ssq dq3 n.c. v ddq dq2 n.c. v ssq dq1 n.c. v ddq v dd a3 a2 a1 a0 a10/ap dq0 v dd v dd ba1 ba0 cs ras we cas n.c. v dd n.c. v ssq dq1 n.c. v ddq n.c. n.c. v ssq dq0 n.c. v ddq v dd a3 a2 a1 a0 a10/ap n.c. v ss n.c. a8 a7 a6 a5 a4 v ss v ssq n.c. dq3 v ddq n.c. n.c. v ssq n.c. dq2 v ddq n.c. v ss n.c. clk dqm cke a12 a11 a9 a9 a11 a12 cke dqm clk n.c. v ss n.c. v ddq dq4 n.c. v ssq dq5 n.c. v ddq dq6 n.c. v ssq v ss a4 a5 a6 a7 a8 dq7 v ss v ss a9 a11 a12 cke udqm clk n.c. v ss dq8 v ddq dq9 dq10 v ssq dq11 dq12 v ddq dq13 dq14 v ssq v ss a4 a5 a6 a7 a8 dq15 tsopii-54 (400 mil x 875 mil, 0.8 mm pitch) 64mx4 32mx8 16mx16
infineon technologies 4 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram pinouts (tfbga-54) pin configuration for x16 devices: pin configuration for x8 devices: pin configuration for x4 devices: 123 789 vss dq15 vssq a vddq dq0 vdd dq14 dq13 vddq b vssq dq2 dq1 dq12 dq11 vssq c vddq dq4 dq3 dq10 dq9 vddq d vssq dq6 dq5 dq8 nc vss e vdd ldqm dq7 udqm clk cke f cas ras we a12 a11 a9 g ba0 ba1 cs a8 a7 a6 h a0 a1 a10 vss a5 a4 j a3 a2 vdd 123 789 vss dq7 vssq a vddq dq0 vdd nc dq6 vddq b vssq dq1 nc nc dq5 vssq c vddq dq2 nc nc dq4 vddq d vssq dq3 nc nc nc vss e vdd nc nc dqm clk cke f cas ras we a12 a11 a9 g ba0 ba1 cs a8 a7 a6 h a0 a1 a10 vss a5 a4 j a3 a2 vdd 123 789 vss nc vssq a vddq nc vdd nc dq3 vddq b vssq dq0 nc nc nc vssq c vddq nc nc nc dq2 vddq d vssq dq1 nc nc nc vss e vdd nc nc dqm clk cke f cas ras we a12 a11 a9 g ba0 ba1 cs a8 a7 a6 h a0 a1 a10 vss a5 a4 j a3 a2 vdd
infineon technologies 5 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram pinout for x4, x8 & x16 organised 256m-drams block diagram for 64m x 4 sdram ( 13 / 11 / 2 addressing) memory array bank 1 8192 x2048 x4bit memory array bank 2 8192 x2048 x4bit memory array bank 3 8192 x2048 x4bit spb04127_2 column address counter row decoder memory array bank 0 8196 x2048 x4bit column decoder sense amplifier &i(o)bus row decoder sen se amplifier & i(o) bus row decoder row decoder column decoder sense amplifier & i(o) bus row address buffer column address b u ffe r refresh counter sense amplifier & i(o) bus a0 - a12, ba0, ba1 a0 - a9, a11, ap, ba0, ba1 colum n addresses row addresses in p ut b u ffe r output buffer dq0 - dq3 control logic & timing generator clk cke cs ras cas we dqm column decode r colu mn decoder
infineon technologies 6 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram block diagram for 32m x 8 sdram ( 13 / 10 / 2 addressing) memory array bank 1 8192 x 1024 x 8 bit memory array bank 2 8192 x 1024 x 8 bit memory array bank 3 8192 x 1024 x 8 bit spb04128 column address counter row decoder memory array bank 0 8192 x 1024 x 8 bit column decoder sense amplifier & i(o) bus row decoder sense amplifier & i(o) bus row decoder row decoder column decoder sense amplifier & i(o) bus row address buffer column address buffer refresh counter sense amplifier & i(o) bus a0 - a12, ba0, ba1 a0 - a9, ap, ba0, ba1 column addresses row addresses input buffer output buffer dq0 - dq7 control logic & timing generator clk cke cs ras cas we dqm column decoder column decoder
infineon technologies 7 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram block diagram for 16m x16 sdram ( 13 / 9 / 2 addressing) memory array bank 1 8192 x 512 x16bit memory array bank 2 8192 x 512 x16bit memory array bank 3 8192 x 512 x16bit spb04129 column address counter row decoder memory array bank 0 8192 x 512 x16bit column decoder sense amplifier & i(o) bus row decoder sense amplifier & i(o) bus row decoder row decoder column decoder sense amplifier & i(o) bus row address buffer column address buffer refresh counter sense amplifier & i(o) bus a0 - a12, ba0, ba1 a0 - a8, ap, ba0, ba1 column addresses row addresses input buffer output buffer dq0 - dq15 control logic & timing generator clk cke cs ras cas we dqmu dqml column decoder column decoder
infineon technologies 8 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram signal pin description pin type signal polarity function clk input pulse positive edge the system clock input. all of the sdram inputs are sampledontherisingedgeoftheclock. cke input level active high activates the clk signal when high and deactivates the clk signal when low, thereby initiating either the power down mode, suspend mode, or the self refresh mode. cs input pulse active low cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras cas we input pulse active low when sampled at the positive rising edge of the clock, cas ,ras ,andwe define the command to be executed by the sdram. a0 - a12 input level ? during a bank activate command cycle, a0-a12 define the row address (ra0-ra12) when sampled at the rising clock edge. during a read or write command cycle, a0-an define the column address (ca0-can) when sampled at the rising clock edge.can depends upon the sdram organization: 64m x4 sdram can = ca9, ca11 (page length = 2048 bits) 32m x8 sdram can = ca9 (page length = 1024 bits) 16m x16 sdram can = ca8 (page length = 512 bits) in addition to the column address, a10(= ap) is used to invoke the autoprecharge operation at the end of the burst read or write cycle. if a10 is high, autoprecharge is selected and ba0, ba1 defines the bank to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10 (= ap) is used in conjunction with ba0 and ba1 to control which bank(s) to precharge. if a10 is high, all four banks will be precharged regardless of the state of ba0 and ba1. if a10 is low, then ba0 and ba1 are used to define which bank to precharge. ba0, ba1 input level ? bank select inputs. bank address inputs selects which of the four banks a command applies to. dqx input output level ? data input/output pins operate in the same manner as on conventional drams.
infineon technologies 9 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram dqm ldqm udqm input pulse active high the data input/output mask places the dq buffers in a high impedance state when sampled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if dqm is high. one dqm input is present in x4 and x8 sdrams, ldqm and udqm controls the lower and upper bytes in x16 sdrams. v dd v ss supply ? ? power and ground for the input buffers and the core logic. v ddq v ssq supply ? ? isolated power supply and ground for the output buffers to provide improved noise immunity. pin type signal polarity function
infineon technologies 10 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram operation definition all of sdram operations are defined by states of control signals cs ,ras ,cas ,we ,anddqmat the positive edge of the clock. the following list shows the truth table for the operation commands. operation device state cke n-1 cke n dqm ba0 ba1 ap= a10 addr . cs ras cas we bank active idle 3 hxxvvvl lhh bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active 3 hxxvlvlhl l write with autoprecharge active 3 hxxvhvlhl l read active 3 hxxvlvlhlh read with autoprecharge active 3 hxxvhvlhlh mode register set idle h x x v v v l l l l no operation any h x x x x x l h h h burststop active hxxxxxlhhl devicedeselect any hxxxxxhxxx auto refresh idle h h x x x x l l l h self refresh entry idle h l x x x x l l l h self refresh exit idle (self refr.) lhxxxx hxxx lhhx clock suspend entry active h l x x x x x x x x power down entry (precharge or active standby) idle hlxxxx hxxx active 4 lhhh clocksuspendexit active lhxxxxxxxx power down exit any (power down) lhxxxx hxxx lhhl data write/output enable active h x l x x x x x x x data write/output disable active h x h x x x x x x x notes 1. v = valid, x = don?t care, l = low level, h = high level 2. cken signal is input level when commands are provided, cken-1 signal is input level one clock before the commands are provided. 3. this is the state of the banks designated by ba0, ba1 signals. 4. power down mode can not be entered in a burst cycle. when this command asserted in the burst mode cycle device is in clock suspend mode.
infineon technologies 11 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram mode register set table a11 a3 a4 a2 a1 a0 a10 a9 a8 a7 a6 a5 address bus (ax) bt burst length cas latency mode register (mx) cas latency m6 m5 m4 latency 0 0 0 reserved 0 0 1 reserved 010 2 011 3 100 reserved 101 110 111 burst length m2 m1 m0 length sequential interleave 000 1 1 001 2 2 010 4 4 011 8 8 100 reserved reserved 101 110 111fullpage burst type m3 type 0 sequential 1 interleave operation mode m9 mode 0 burst read / burst write 1 burst read / single write operation mode ba0 ba1 a12
infineon technologies 12 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram power on and initialization the default power on state of the mode register is supplier specific and may be undefined. the following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. like a conventional dram, the synchronous dram must be powered up and initialized in a predefined manner. during power on, all vdd and vddq pins must be built up simultaneously to the specified voltage when the input signals are held in the ?nop? state. the power on voltage must not exceed vdd+0.3v on any of the input pins or vdd supplies. the clk signal must be started at the same time. after power on, an initial pause of 200 sisrequired followed by a precharge of all banks using the precharge command. to prevent data contention on the dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. a minimum of eight auto refresh cycles (cbr) are also required.these may be done before or after programming the mode register. failure to follow these steps may lead to unpredictable start-up modes. programming the mode register the mode register designates the operation mode at the read or write cycle. this register is divided into four fields. first, a burst length field which sets the length of the burst, second, an addressing selection bit which programs the column access sequence in a burst cycle (interleaved or sequential). third, a cas latency field to set the access time at clock cycle. fourth, an operation mode field to differentiate between normal operation (burst read and burst write) and a special burst read and single write mode. after the initial power up, the mode set operation must be done before any activate command. any content of the mode register can be altered by re- executing the mode set command. all banks must be in precharged state and cke must be high at least one clock before the mode set operation. after the mode register is set, a standby or nop command is required. low signals of ras ,cas ,andwe at the positive edge of the clock activate the mode set operation. address input data at this timing defines parameters to be set as shown in the previous table. read and write operation when ras is low and both cas and we are high at the positive edge of the clock, a ras cycle starts. according to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. a cas cycle is triggered by setting ras high and cas low at a clock timing after a necessary delay, t rcd ,fromtheras timing. we is used to define either aread(we =h)orawrite(we = l) at this stage. sdram provides a wide variety of fast access modes. in a single cas cycle, serial data read or write operations are allowed at up to a 166 mhz data rate. the numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4 and 8 and full page. column addresses are segmented by the burst length and serial data accesses are done within this boundary. the first column address to be accessed is supplied at the cas timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. for example, in a burst length of 8 with interleave sequence, if the first address is ?2?, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. full page burst operation is only possible using the sequential burst type and page length is a function of the i/o organization and column addressing. full page burst operation does not self
infineon technologies 13 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram terminate once the burst length has been reached. in other words, unlike burst lengths of 2, 4 and 8, full page burst continues until it is terminated using another command. similar to the page mode of conventional drams, burst read or write accesses on any column address are possible once the ras cycle latches the sense amplifiers. the maximum t ras or the refresh interval time limits the number of random column accesses. a new burst access can be done even before the previous burst ends. the interrupt operation at every clock cycle is supported. when the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. an interrupt which accompanies an operation change from a read to a write is possible by exploiting dqm to avoid bus contention. when two or more banks are activated sequentially, interleaved bank read or write operations are possible. with the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. once two or more banks are activated, column to column interleave operation can be performed between different pages. burst length and sequence: refresh mode sdram has two refresh modes, auto refresh and self refresh. auto refresh is similar to the cas -before-ras refresh of conventional drams. all banks must be precharged before applying any refresh mode. an on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. the chip enters the auto refresh mode, when ras and cas are held low and cke and we areheldhighataclocktiming.themoderestoreswordlineaftertherefreshandnoexternal precharge command is necessary. a minimum trc time is required between two automatic refreshes in a burst refresh mode. the same rule applies to any access command after the automatic refresh operation. burst length starting address (a2 a1 a0) sequential burst addressing (decimal) interleave burst addressing (decimal) 2 xx0 xx1 0, 1 1, 0 0, 1 1, 0 4x00 x01 x10 x11 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 8 000 001 010 011 100 101 110 111 01234567 12345670 23456701 34567012 45670123 56701234 67012345 70123456 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210 full page nnn cn, cn+1, cn+2 .... not supported
infineon technologies 14 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram the chip has an on-chip timer and the self refresh mode is available. the mode restores the word lines after ras ,cas ,andckearelowandwe is high at a clock timing. all of external control signals including the clock are disabled. returning cke to high enables the clock and initiates the refresh exit operation. after the exit command, at least one trc delay is required prior to any access command. dqm function dqm has two functions for data i/o read and write operations. during reads, when it turns to ?high? at a clock timing, data outputs are disabled and become high impedance after two clock delay (dqm data disable latency t dqz ). it also provides a data mask function for writes. when dqm is activated, the write operation at the next clock is prohibited (dqm write mask latency t dqw =zero clocks). suspend mode during normal access mode, cke is held high enabling the clock. when cke is low, it freezes the internal clock and extends data read and write operations. one clock delay is required for mode entry and exit (clock suspend latency t csl ). power down in order to reduce standby power consumption, a power down mode is available. all banks must be precharged and the necessary precharge delay (trp) must occur before the sdram can enter the power down mode. once the power down mode is initiated by holding cke low, all of the receiver circuits except clk and cke are gated off. the power down mode does not perform any refresh operations, therefore the device can?t remain in power down mode longer than the refresh period (tref) of the device. exit from this mode is performed by taking cke ?high?. one clock delay is required for power down mode entry and exit. auto precharge two methods are available to precharge sdrams. in an automatic precharge mode, the cas timing accepts one extra address, ca10, to determine whether the chip restores or not after the operation. if ca10 is high when a read command is issued, the read with auto-precharge function is initiated. if ca10 is high when a write command is issued, the write with auto- precharge function is initiated. the sdram automatically enters the precharge operation a time delay equal to t wr (?write recovery time?) after the last data in. a burst operation with auto-precharge may only be interrupted by a burst start to another bank. it must not be interrupted by a precharge or a burst stop command. precharge command there is also a separate precharge command available. when ras and we are low and cas is high at a clock timing, it triggers the precharge operation. three address bits, ba0, ba1 and a10 are used to define banks as shown in the following list. the precharge command can be imposed one clock before the last data out for cas latency = 2 and two clocks before the last data out for cas latency = 3. writes require a time delay twr (?write recovery time?) of 2 clocks minimum from the last data out to apply the precharge command.
infineon technologies 15 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram bank selection by address bits burst termination once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. these methods include using another read or write command to interrupt an existing burst operation, use a precharge command to interrupt a burst cycle and close the active bank, or using the burst stop command to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank. when interrupting a burst with another read or write command care must be taken to avoid dq contention. the burst stop command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. if a burst stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. data that is presented on the dq pins before the burst stop command is registered will be written to the memory. capacitance t a =0to70 c; v dd, v ddq =3.3v 0.3 v, f =1mhz a10 ba0 ba1 0 0 0 bank 0 0 0 1 bank 1 0 1 0 bank 2 0 1 1 bank 3 1xx allbanks parameter symbol values unit min. max. input capacitance (clk) c i 1 2.5 3.5 pf input capacitance (a0-a12, ba0,ba1,ras ,cas ,we ,cs ,cke,dqm) c i 2 2.5 3.8 pf input / output capacitance (dq) c i o 4.0 6.0 pf note: capacitance values are shown for tsop-54 packages. capacitance values for tfbga packages are lower by 0.5 pf.
infineon technologies 16 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram absolute maximum ratings recommended operation conditions and dc eletrical characteristics t a =0to70 o c; parameter symbol limit values unit min. max. input / output voltage relative to v ss v in, v out ?1.0 4.6 v power supply voltage v dd, v ddq ?1.0 4.6 v operating temperature t a 0+70 o c storage temperature range t stg -55 +150 o c power dissipation per sdram component p d ?1w data out current (short circuit) i os ?50ma permanent device damage may occur if ?absolute maximum ratings? are exceeded. functional operation should be restricted to recommended operation conditions. exposure to higher than recommended voltage for extended periods of time affect device reliability parameter symbol limit values unit notes min. typ. max. supply voltage v dd, v ddq 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 3.0 v ddq +0.3 v 1, 2 input low voltage v il ? 0.3 0 0.8 v 1, 2 output high voltage ( i out =?4.0ma) v oh 2.4 ? ? v 1 output low voltage ( i out =4.0ma) v ol ?? 0.4v1 input leakage current, any input (0 v < v in < v dd , all other inputs = 0 v) i il ?5 ? 5 ma output leakage current (dqs are disabled, 0 v < v out < v ddq ) i ol ?5 ? 5 ma notes: 1. all voltages are referenced to v ss . 2. vih may overshoot to v ddq + 2.0 v for pulse width of < 4ns with 3.3v. vil may undershoot to -2.0 v for pulse width < 4.0 ns with 3.3v. pulse width measured at 50 % points with amplitude measured peak to dc reference.
infineon technologies 17 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram operating currents t a =0to70 o c; v ss =0v;v dd ,v ddq =3.3v 0.3 v parameter & test condition symb. -6 -7 -7.5 -8 note max. operating current one bank active, burst length = 1 t rc =t rc(min) , io = 0 ma idd1 100 80 80 80 ma 3, 4 precharge standby current in power down mode cs =vih (min.), cke < =vil(max) idd2p2222ma3 precharge standby current in non-power down mode cs =vih(min.), cke > =vih(min) idd2n 35 30 30 25 ma 3 no operating current active state ( max. 4 banks) cs =vih(min), cke > =vih(min.) idd3n 40 35 35 30 ma 3 cs =vih(min), cke < =vil(max.) idd3p5555ma3 burst operating current read command cycling idd4 110 90 90 70 ma 3, 4 auto refresh current auto refresh command cycling t rfc =t rfc(min) idd5 220 190 190 160 ma 5 t rfc =7.8 s 3333ma self refresh current (standard components) self refresh mode, cke=0.2v, tck=infinity x4, x8 x16 idd6 3 1.5 3 1.5 3 1.5 3 1.5 ma ma self refresh current (low power components) self refresh mode, cke=0.2v, tck=infinity x8, x16 idd6 0.85 0.85 0.85 0.85 ma notes: 3. these parameters depend on the cycle rate. all values are measured at 166 mhz for ?-6?, at 133 mhz for ?-7? and ?-7.5? and at 100 mhz for ?-8? components with the outputs open. input signals are changed once during tck. 4. these parameters are measured with continuous data stream during read access and all dq toggling. cl=3 and bl=4 is assumed and the vddq current is excluded. 5. t rfc =t rfc(min) ?burst refresh?, t rfc =7.8 s ?distributed refresh?.
infineon technologies 18 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram ac characteristics 1)2) t a =0to70 o c; v ss =0v;v dd ,v ddq =3.3v 0.3v, tt=1ns parameter symbol limit values unit -6 pc166- 333 -7 pc133- 222 -7.5 pc133- 333 -8 pc100- 222 min. max. min. max. min. max. min. max. clock and clock enable clock cycle time cas latency = 3 cas latency = 2 t ck 6 7.5 ? ? 7 7.5 ? ? 7.5 10 ? ? 8 10 ? ? ns ns clock frequency cas latency = 3 cas latency = 2 t ck ? ? 166 133 ? ? 143 133 ? ? 133 100 ? ? 125 100 mhz mhz access time from clock cas latency = 3 cas latency = 2 t ac ? ? 5 5.4 ? ? 5.4 5.4 ? ? 5.4 6 ? ? 6 6 ns ns 2, 3, 6 clock high pulse width t ch 2 ? 2.5 ? 2.5 ? 3 ? ns clock low pulse width t cl 2 ? 2.5 ? 2.5 ? 3 ? ns transition time t t 0.3 1.2 0.3 1.2 0.3 1.2 0.5 10 ns setup and hold times input setup time t is 1.5 ? 1.5 ? 1.5 ? 2 ? ns 4 input hold time t ih 0.8 ? 0.8 ? 0.8 ? 1 ? ns 4 cke setup time t cks 1.5 ? 1.5 ? 1.5 ? 2 ? ns 4 cke hold time t ckh 0.8 ? 0.8 ? 0.8 ? 1 ? ns 4 mode register set-up to active delay t rsc 2?2?2?2?clk power down mode entry time t sb 060707.508ns common parameters row to column delay time t rcd 15?15?20?20?ns 5 row precharge time t rp 15?15?20?20?ns 5 row active time t ras 36 100k 37 100k 45 100k 48 100k ns 5 row cycle time t rc 60?60?67?70 ? ns 5
infineon technologies 19 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram row cycle time during auto refresh t rfc 60 63 67 70 ns activate(a) to activate(b) command period t rrd 12?14?15?16?ns 5 cas (a) to cas (b) command period t ccd 1?1?1?1?clk refresh cycle refresh period (8192 cycles) t ref ?64?64?64?64ms self refresh exit time t srex 1?1?1?1 clk read cycle data out hold time t oh 2.5?3?3?3?ns2, 6 data out to low impedance time t lz 0?0?0?0?ns data out to high impedance time t hz 36373738ns dqm data out disable latency t dqz ?2?2?2?2clk write cycle last data input to precharge (write without autoprecharge) t wr 12?14?15?15?ns 7 last data input to activate (write with autoprecharge) t dal,min (twr/tck) + (trp/tck) clk 8 dqm write mask latency t dqw 0?0?0?0?clk parameter symbol limit values unit -6 pc166- 333 -7 pc133- 222 -7.5 pc133- 333 -8 pc100- 222 min. max. min. max. min. max. min. max.
infineon technologies 20 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram notes 1. for proper power-up see the operation section of this data sheet. 2. ac timing tests for lv-ttl versions have v il =0.4vand v ih = 2.4 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il .allac measurements assume t t = 1 ns with the ac output load circuit shown in figure below. specified t ac and t oh parameters are measured with a 50 pf only, without any resistive termination and with an input signal of 1v / ns edge rate between 0.8 v and 2.0 v. 3. if clock rising time is longer than 1 ns, a time ( t t /2 ? 0.5) ns has to be added to this parameter. 4. if t t is longer than 1 ns, a time ( t t ? 1) ns has to be added to this parameter. 5. these parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows: thenumberofclockcycles=specifiedvalueoftimingperiod(countedinfractionsasawhole number) 6. access time from clock t ac is 4.6 ns for pc133 components with no termination and 0 pf load, data out hold time t oh is 1.8 ns for pc133 components with no termination and 0 pf load. 7. it is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command without auto-precharge. one clock cycle between the last data-in and the precharge command is also supported, but restricted to cycle times tck greater or equal the specified twr value, where tck is equal to the actual system clock time 8. when a write command with autoprecharge has been issued, a time of tdal(min) has be fullfilled before the next activate command can be applied. for each of the terms, if not already an integer, round up to the next highest integer. tck is equal to the actual system clock time. 50 pf i/o measurement conditions for t ac and t oh clock 2.4 v 0.4 v input is t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t ih t 1.4 v io.vsd
infineon technologies 21 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram package outlines - tsop gpx09039 22.22 ?.13 1) 127 54 28 0.35 +0.1 -0.05 0.1 1 0.1 10.16 ?.13 ?.2 11.76 ?.1 0.5 does not include plastic or metal protrusion of 0.15 max per side 1) 54x ?.05 ?.05 0.15 -0.03 +0.06 15? ?? 15? ?? 6 max 2.5 max 2) 3) does not include plastic protrusion of 0.25 max per side 2) does not include dambar protrusion of 0.13 max per side 3) index marking 0.8 20.8 26x 0.8 = 0.2 m 54x plastic package p-tsopii-54 (400 mil, 0.8 mm lead pitch) thin small outline package, smd
infineon technologies 22 2002-04-23 hyb39s256400/800/160dt(l)/dc(l) 256mbit synchronous dram package outlines- tfbga tfbga-54 package (12 mm x 8 mm, 54 balls)

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